System and method for concurrent placement of gates and associated wiring
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United States of America Patent
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May 7, 2002
Grant Date -
Nov 29, 2001
app pub date -
Jun 12, 1998
filing date -
Jun 12, 1998
priority date (Note) -
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Abstract
A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.
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