Method of manufacturing a semiconductor device

United States of America Patent

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May 14, 2002
Grant Date
Mar 21, 2002
app pub date
Sep 30, 1999
filing date
Oct 5, 1998

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Expired

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Abstract

In a method of manufacturing a semiconductor device having a multi-layer interconnection, after a via hole has been formed, the inside of the via hole is cleaned using a cleaning solution containing a complexing agent capable of forming a complex with contaminants of copper type metals.

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Patent Owner(s)

Patent Owner	Address
RENESAS ELECTRONICS CORPORATION	2-24 TOYOSU 3-CHOME KOTO-KU TOKYO 135-0061

International Classification(s)

H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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[Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Aoki, Hidemitsu	Tokyo, JP	79	1177

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Method of manufacturing a semiconductor device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

09409143

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PATENT NO	6387821
APP PUB NO	20020034874A1
SERIAL NO	09409143
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity Expired	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
May 14, 2002	US,6387821,B1 US6387821B1	GRANTED PATENT AS FIRST PUBLICATION
March 21, 2002	US,20020034874,A1 US20020034874A1	FIRST PUBLISHED PATENT APPLICATION

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09409143

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