Nonvolatile memory cell, operating method of the same and nonvolatile memory array
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United States of America Patent
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May 14, 2002
Grant Date -
N/A
app pub date -
Jun 16, 2000
filing date -
Oct 12, 1999
priority date (Note) -
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Abstract
The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n.sup.+ region 121 and a second n.sup.+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n.sup.+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n.sup.+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.
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