Method and apparatus for reducing the lock time of DLL
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 14, 2002
Grant Date -
N/A
app pub date -
Aug 28, 2000
filing date -
Aug 30, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay element. When the first pulse reaches the end of the delay line, the status of the shift bits is frozen, and a starting point for a synchronization sequence begins at the transition point between toggled and retoggled shift bits.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully