Importance

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Abstract

A controllable ring oscillator clock circuit includes a plurality of ring oscillator stages disposed in a linear chain. Each stage has a latch that determines if this stage is the last stage in the ring. In a propagate state of the latch the ring pulse is sent to the next stage. In a return state of the latch the ring pulse is returned to the prior stage. The latches are programmed like a shift register. A more command transfers the propagate state to the next stage. This increases the length of the delay line and thus decreases the oscillator frequency. A less command transfers the return state to the prior state, decreasing the ring delay and increasing the oscillator frequency. In the preferred embodiment the delay stages are deployed as even and odd pairs with only the even or the odd stages changed at one time. This enables a simple structure because the pairs operate like a master-slave flip-flop, that is the data can move only a single stage at a time.

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First Claim