Divide-by-three circuit
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United States of America Patent
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-
May 14, 2002
Grant Date -
N/A
app pub date -
Oct 27, 2000
filing date -
Oct 27, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
An in-phase clock signal CLK_I drives a first pair of connected data flip-flops (DFFs) (302) and (308), with feedback through a NOR gate (310) and output through an in-phase OR gate (320). The output signal OUT_I is a clock signal with a third of the frequency of CLK_I. A quadrature-phase clock signal CLK_Q drives a second pair of (DFFs) (504) and (506), with output through a quadrature OR gate (508). The output signal OUT_Q is a clock signal with a third of the frequency of CLK_Q, and in quadrature with OUT_I.
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