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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
FUJITSU LIMITED	1-1 KAMIKODANAKA 4-CHOME NAKAHARA- KU KAWASAKI-SHI KANAGAWA 211-8588 211-8588

International Classification(s)

• H05K:PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAIL....

• [Classification Symbol]

• [Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Iida, Kenji	Kawasaki, JP	94	568
Katayama, Hiroyuki	Kawasaki, JP	235	1770
Katsube, Toshiro	Yonago, JP	4	29
Kurokawa, Yasunaga	Kawasaki, JP	3	14
Nakano, Kazuo	Kawasaki, JP	37	434
Ohta, Yuichiro	Yonago, JP	9	61
Ozaki, Norikazu	Kawasaki, JP	37	268
Sumi, Masaru	Yonago, JP	3	14
Takahashi, Yasuhito	Kawasaki, JP	49	1708

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
May 21, 2002	US,6389686,B2   US6389686B2	GRANTED PATENT AS SECOND PUBLICATION
August 23, 2001	US,20010015008,A1   US20010015008A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 6389686

Process for fabricating a thin multi-layer circuit board

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