Wafer level interposer
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United States of America Patent
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-
May 21, 2002
Grant Date -
N/A
app pub date -
Nov 16, 1999
filing date -
Nov 16, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An apparatus and method for manufacture and testing of semiconductor chips (14) is disclosed. The invention comprises the use of an interposer (22) having a plurality of electrical contact pads (26) on each surface connected by a plurality of conductors (32, 34). After assembly of the interposer (22) to a semiconductor wafer (12), the wafer-interposer assembly (10) is attached to a testing unit (46) wherein the semiconductor chips (14) on the wafer (12) are tested. After testing, the interposer-wafer assembly (10) is singulated into a plurality of chip assemblies (62), each chip assembly (62) comprising a silicon chip (64) and the permanently attached interposer (66).
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