Expandable interconnect structure for FPGAS
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United States of America Patent
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May 28, 2002
Issued Date -
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app pub date -
Jul 27, 1999
filing date -
Feb 26, 1997
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Abstract
The programmable interconnect points (PIPS) associated with each tile of an FPGA are programmed in response to configuration data values stored in an array of configuration memory cells. Configuration memory cells that control the configuration of the interconnect structure of the tile are located in a rectangular block within the array. For example, the configuration memory cells that control the configuration of the interconnect structure may be located in several rows of the array. This configuration enables the interconnect structure of the tile to be easily modified. To add more interconnect lines to the FPGA, the additional interconnect lines and their associated PIPs are added to the interconnect structure, and the configuration memory cells required to program the PIPs are added as additional rows in the configuration memory cell array. The pattern of configuration memory cells remains unchanged, except for the added rows of configuration memory cells. As a result, the stream of configuration data values required to program the original FPGA is compatible with the stream of configuration data values required to program the FPGA having the expanded interconnect 'structure.
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- XILINX, INC.
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Young, Steven P | San Jose, CA | 216 | 7862 |
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