Process for fabricating a planar heterostructure

United States of America Patent

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Jun 4, 2002
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N/A
app pub date
Mar 31, 2000
filing date
Mar 31, 1999

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Expired

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Abstract

The process comprises: etching, in a semiconductor substrate (2), at least one trench (3) with predetermined width and depth; depositing, on the substrate and in the trench, a stack of successive and alternate layers of Si.sub.1-x Ge.sub.x (0

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Patent Owner	Address
FAHRENHEIT THERMOSCOPE LLC	2215-B RENAISSANCE DRIVE SUITE 5 LAS VEGAS NV 89119

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H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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Inventor Name	Address	# of filed Patents	Total Citations
Bensahel, Daniel	Grenoble, FR	32	486
Campidelli, Yves	Grenoble, FR	24	353
Hernandez, Caroline	Grenoble, FR	15	314
Rivoire, Maurice	Meylan, FR	22	246

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Process for fabricating a planar heterostructure

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United States of America Patent

09540188

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PATENT NO	6399502
SERIAL NO	09540188
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09540188

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