US Patent No: 6,400,004

Number of patents in Portfolio can not be more than 2000

Leadless semiconductor package

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Abstract

A leadless semiconductor package mainly comprises a semiconductor chip disposed on a die pad and electrically connected to a plurality of leads arranged around the die pad. There are a plurality of tie bars connected to the die pad. The lower surface of each lead has an indentation formed corresponding to one of the bottom edges of the package. The semiconductor chip, the leads and the tie bars are encapsulated in a package body wherein the lower surface of each lead is exposed from the bottom surface of the package except the indentation thereof.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ADVANCED SEMICONDUCTOR ENGINEERING, INC.KAOHSIUNG706

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Daniel Torrance, CA 40 323
Chiu, Rick Taoyuan, TW 3 181
Chiu, Roger Hsinchu Hsien, TW 1 176
Fan, Alex Taoyuan, TW 1 176
Kuo, Jack Jungli, TW 13 196
Li, Jim San Jose, CA 32 221

Cited Art

Patent Info (Count) # Cites Year
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (2)
6,166,430 Lead frame, method for manufacturing the frame, resin-molded semiconductor device and method for manufacturing the device 81 1999
6,208,020 Leadframe for use in manufacturing a resin-molded semiconductor device 174 1999
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
5,894,108 Plastic package with exposed die 250 1997

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
AMKOR TECHNOLOGY, INC. (123)
7,102,208 Leadframe and semiconductor package with improved solder joint strength 2 2000
7,102,216 Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making 4 2001
6,885,086 Reduced copper lead frame for saw-singulated chip package 8 2002
6,608,366 Lead frame with plated end leads 20 2002
6,919,620 Compact flash memory card with clamshell leadframe 1 2002
6,798,047 Pre-molded leadframe 5 2002
6,777,789 Mounting for a package containing a chip 6 2003
6,965,159 Reinforced lead-frame assembly for interconnecting circuits within a circuit module 4 2003
6,750,545 Semiconductor package capable of die stacking 13 2003
6,794,740 Leadframe package for semiconductor devices 4 2003
7,095,103 Leadframe based memory card 0 2003
6,879,034 Semiconductor package including low temperature co-fired ceramic substrate 4 2003
7,045,396 Stackable semiconductor package and method for manufacturing same 77 2003
7,008,825 Leadframe strip having enhanced testability 24 2003
6,876,068 Semiconductor package with increased number of input and output pins 44 2003
7,183,630 Lead frame with plated end leads 7 2003
6,897,550 Fully-molded leadframe stand-off feature 3 2003
7,485,952 Drop resistant bumpers for fully molded memory cards 0 2003
6,873,032 Thermally enhanced chip scale lead on chip semiconductor package and method of making same 11 2003
6,873,041 Power semiconductor package with strap 16 2003
7,071,541 Plastic integrated circuit package and method and leadframe for making the package 1 2003
7,245,007 Exposed lead interposer leadframe package 44 2003
7,057,280 Leadframe having lead locks to secure leads to encapsulant 4 2003
6,921,967 Reinforced die pad support structure 4 2003
6,998,702 Front edge chamfer feature for fully-molded memory cards 7 2003
6,846,704 Semiconductor package and method for manufacturing the same 10 2003
6,967,395 Mounting for a package containing a chip 12 2003
6,893,900 Method of making an integrated circuit package 1 2003
7,138,707 Semiconductor package including leads and conductive posts for providing increased functionality 5 2003
7,144,517 Manufacturing method for leadframe and for semiconductor package using the leadframe 3 2003
7,211,879 Semiconductor package with chamfered corners and method of manufacturing the same 4 2003
6,965,157 Semiconductor package with exposed die pad and body-locking leadframe 9 2003
7,115,445 Semiconductor package having reduced thickness 1 2004
7,057,268 Cavity case with clip/plug for use on multi-media card 3 2004
7,091,594 Leadframe type semiconductor package having reduced inductance and its manufacturing method 7 2004
7,170,150 Lead frame for semiconductor package 2 2004
6,844,615 Leadframe package for semiconductor devices 7 2004
7,005,326 Method of making an integrated circuit package 5 2004
7,190,062 Embedded leadframe semiconductor package 24 2004
7,067,908 Semiconductor package having improved adhesiveness and ground bonding 4 2004
7,211,471 Exposed lead QFP package fabricated through the use of a partial saw process 43 2004
7,598,598 Offset etched corner leads for semiconductor package 0 2004
7,202,554 Semiconductor package and its manufacturing method 14 2004
7,045,882 Semiconductor package including flip chip 7 2004
6,953,988 Semiconductor package 18 2004
7,217,991 Fan-in leadframe semiconductor package 8 2004
7,253,503 Integrated circuit device packages and substrates for making the packages 41 2004
7,001,799 Method of making a leadframe for semiconductor devices 2 2004
7,064,009 Thermally enhanced chip scale lead on chip semiconductor package and method of making same 7 2004
7,030,474 Plastic integrated circuit package and method and leadframe for making the package 2 2004
7,176,062 Lead-frame method and assembly for interconnecting circuits within a circuit module 0 2005
7,214,326 Increased capacity leadframe and semiconductor package using the same 4 2005
7,247,523 Two-sided wafer escape package 15 2005
6,995,459 Semiconductor package with increased number of input and output pins 49 2005
7,192,807 Wafer level package and fabrication method 17 2005
7,045,883 Thermally enhanced chip scale lead on chip semiconductor package and method of making same 5 2005
7,507,603 Etch singulated semiconductor package 8 2005
7,361,533 Stacked embedded leadframe 20 2005
7,572,681 Embedded electronic component package 19 2005
7,112,474 Method of making an integrated circuit package 1 2005
7,564,122 Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant 1 2006
8,410,585 Leadframe and semiconductor package made using the leadframe 0 2006
7,535,085 Semiconductor package having improved adhesiveness and ground bonding 2 2006
7,902,660 Substrate for semiconductor device and manufacturing method thereof 15 2006
7,968,998 Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package 2 2006
7,321,162 Semiconductor package having reduced thickness 0 2006
7,332,375 Method of making an integrated circuit package 0 2006
7,521,294 Lead frame for semiconductor package 5 2006
7,714,431 Electronic component package comprising fan-out and fan-in traces 20 2006
7,687,893 Semiconductor package having leadframe with exposed anchor pads 3 2006
7,829,990 Stackable semiconductor package including laminate interposer 1 2007
7,982,297 Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same 1 2007
7,420,272 Two-sided wafer escape package 16 2007
7,723,210 Direct-write wafer level chip scale package 6 2007
7,977,774 Fusion quad flat semiconductor package 3 2007
7,687,899 Dual laminate package structure with embedded elements 6 2007
7,777,351 Thin stacked interposer package 24 2007
8,089,159 Semiconductor package with increased I/O density and method of making the same 0 2007
7,847,386 Reduced size stacked semiconductor package and method of making the same 0 2007
7,560,804 Integrated circuit package and method of making the same 1 2008
7,956,453 Semiconductor package with patterning layer and method of making same 1 2008
7,723,852 Stacked semiconductor package and method of making same 4 2008
8,067,821 Flat semiconductor package with half package molding 2 2008
7,768,135 Semiconductor package with fast power-up cycle and method of making same 3 2008
7,808,084 Semiconductor package with half-etched locking features 1 2008
8,125,064 Increased I/O semiconductor package and method of making same 0 2008
8,184,453 Increased capacity semiconductor package 1 2008
7,692,286 Two-sided fan-out wafer escape package 20 2008
7,847,392 Semiconductor device including leadframe with increased I/O 5 2008
7,989,933 Increased I/O leadframe and semiconductor device including same 1 2008
8,008,758 Semiconductor device with increased I/O leadframe 3 2008
8,089,145 Semiconductor device including increased capacity leadframe 1 2008
8,072,050 Semiconductor device with increased I/O leadframe including passive device 0 2008
7,875,963 Semiconductor device including leadframe having power bars and increased I/O 3 2008
7,982,298 Package in package semiconductor device 1 2008
8,058,715 Package in package device for RF transceiver module 1 2009
7,732,899 Etch singulated semiconductor package 0 2009
8,026,589 Reduced profile stackable semiconductor package 5 2009
7,960,818 Conformal shield on punch QFN semiconductor package 0 2009
7,928,542 Lead frame for semiconductor package 1 2009
7,977,163 Embedded electronic component package fabrication method 2 2009
8,089,141 Semiconductor package having leadframe with exposed anchor pads 0 2010
7,872,343 Dual laminate package structure with embedded elements 1 2010
8,188,584 Direct-write wafer level chip scale package 0 2010
7,932,595 Electronic component package comprising fan-out traces 4 2010
8,324,511 Through via nub reveal method and structure 0 2010
7,906,855 Stacked semiconductor package and method of making same 1 2010
8,294,276 Semiconductor device and fabricating method thereof 0 2010
8,084,868 Semiconductor package with fast power-up cycle and method of making same 0 2010
8,319,338 Thin stacked interposer package 0 2010
8,440,554 Through via connected backside embedded circuit features structure and method 0 2010
8,299,602 Semiconductor device including leadframe with increased I/O 0 2010
8,283,767 Dual laminate package structure with embedded elements 0 2010
8,188,579 Semiconductor device including leadframe having power bars and increased I/O 1 2010
8,390,130 Through via recessed reveal structure and method 0 2011
8,318,287 Integrated circuit package and method of making the same 0 2011
8,102,037 Leadframe for semiconductor package 0 2011
8,119,455 Wafer level package fabrication method 1 2011
8,441,110 Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package 0 2011
8,304,866 Fusion quad flat semiconductor package 0 2011
8,432,023 Increased I/O leadframe and semiconductor device including same 0 2011
8,227,921 Semiconductor package with increased I/O density and method of making same 0 2011
8,298,866 Wafer level package and fabrication method 0 2012
 
NATIONAL SEMICONDUCTOR CORPORATION (9)
6,888,228 Lead frame chip scale package 4 2000
6,674,156 Multiple row fine pitch leadless leadframe package with use of half-etch process 19 2001
6,710,246 Apparatus and method of manufacturing a stackable package for a semiconductor device 15 2002
RE39854 Lead frame chip scale package 4 2002
6,723,585 Leadless package 27 2002
6,872,599 Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) 11 2002
7,002,239 Leadless leadframe packaging panel featuring peripheral dummy leads 6 2003
7,432,583 Leadless leadframe package substitute and stack package 0 2004
7,023,074 Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) 4 2005
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (7)
6,603,194 Lead frame and method for fabricating resin-encapsulated semiconductor device using the same 7 2001
6,645,792 Lead frame and method for fabricating resin-encapsulated semiconductor device 5 2001
6,909,168 Resin encapsulation semiconductor device utilizing grooved leads and die pad 4 2002
6,835,600 Lead frame and method for fabricating resin-encapsulated semiconductor device using the same 2 2003
7,132,733 Semiconductor device 3 2004
7,338,838 Resin-encapsulation semiconductor device and method for fabricating the same 1 2005
7,397,113 Semiconductor device 2 2006
 
MICRON TECHNOLOGY, INC. (5)
7,294,911 Ultrathin leadframe BGA circuit package 3 2002
7,109,572 Quad flat no lead (QFN) grid array package 33 2003
7,075,816 Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same 25 2003
7,183,134 Ultrathin leadframe BGA circuit package 5 2004
7,279,780 Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same 3 2005
 
PANASONIC CORPORATION (4)
D600219 Lead frame 0 2006
7,589,404 Semiconductor device 5 2008
7,939,933 Semiconductor device 3 2009
8,178,955 Semiconductor device 0 2011
 
STATS CHIPPAC LTD. (4)
7,645,640 Integrated circuit package system with leadframe substrate 3 2005
7,498,665 Integrated circuit leadless package system 0 2006
7,936,053 Integrated circuit package system with lead structures including a dummy tie bar 0 2006
8,174,120 Integrated circuit package system with leadframe substrate 0 2009
 
CHIPMOS TECHNOLOGIES INC. (3)
7,902,649 Leadframe for leadless package, structure and manufacturing method using the same 0 2007
8,105,876 Leadframe for leadless package, structure and manufacturing method using the same 0 2011
8,106,494 Leadframe for leadless package, structure and manufacturing method using the same 0 2011
 
DAI NIPPON PRINTING CO., LTD. (3)
6,744,118 Frame for semiconductor package 4 2001
6,882,048 Lead frame and semiconductor package having a groove formed in the respective terminals for limiting a plating area 9 2002
6,897,549 Frame for semiconductor package 0 2003
 
ROHM CO., LTD. (2)
6,709,892 Electronic device fabrication method comprising twofold cutting of conductor member 4 2002
7,364,947 Method for cutting lead terminal of package type electronic component 0 2003
 
UTAC THAI LIMITED (2)
8,367,476 Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide 0 2009
8,431,443 Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide 0 2011
 
ADVANCED MICRO DEVICES, INC. (1)
6,661,102 Semiconductor packaging apparatus for controlling die attach fillet height to reduce die shear stress 2 2002
 
ADVANCED SEMICONDUCTOR ENGINEERING, INC. (1)
7,378,299 Leadless semiconductor package and manufacturing method thereof 4 2006
 
ALPHA & OMEGA SEMICONDUCTOR, LTD. (1)
7,208,818 Power semiconductor package 10 2004
 
ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED (1)
7,759,775 High current semiconductor power device SOIC package 4 2006
 
APTINA IMAGING CORPORATION (1)
7,095,621 Leadless leadframe electronic package and sensor module incorporating same 4 2003
 
FAIRCHILD KOREA SEMICONDUCTOR LTD. (1)
8,350,369 High power semiconductor package 0 2008
 
FAIRCHILD SEMICONDUCTOR CORPORATION (1)
8,120,169 Thermally enhanced molded leadless package 0 2008
 
NXP B.V. (1)
7,115,443 Method and apparatus for manufacturing a packaged semiconductor device, packaged semiconductor device obtained with such a method and metal carrier suitable for use in such a method 2 2003
 
SAMSUNG TECHWIN CO., LTD. (1)
6,838,753 Lead-frame strip and method of manufacturing semiconductor packages using the same 6 2002
 
TEXAS INSTRUMENTS INCORPORATED (1)
7,741,704 Leadframe and mold compound interlock in packaged semiconductor device 1 2007
 
UNISEM (MAURITIUS) HOLDINGS LIMITED (1)
7,943,431 Leadless semiconductor package and method of manufacture 0 2006
 
UTAC HONG KONG LIMITED (1)
7,049,177 Leadless plastic chip carrier with standoff contacts and die attach pad 48 2004
 
VISERA TECHNOLOGIES COMPANY LIMITED (1)
7,737,538 Semiconductor package 0 2007
 
YAMAHA CORPORATION (1)
7,397,112 Semiconductor package and lead frame therefor 1 2005

Maintenance Fees

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11.5 Year Payment $7400.00 $3700.00 $1850.00 Dec 4, 2013
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Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00