Clamp circuit to prevent ESD damage to an integrated circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Jun 4, 2002
Grant Date -
N/A
app pub date -
Mar 11, 2000
filing date -
Mar 12, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In an integrated circuit device requiring electrostatic discharge (ESD) protection, a circuit is added between a power supply bus and a ground supply bus to shunt the ESD event current and thereby avoiding damage to the device. Specifically, the circuit uses bipolar junction transistors of the PNP type to shunt the supply buses. The emitter junctions are connected to the positive supply bus. The collector junctions are connected to the ground bus. The PNP transistors conduct when a control circuit senses an ESD event and increases the base current in the PNP transistor.
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