Importance

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Abstract

A glitchless delay line using a Gray code multiplexer is provided. The glitchless delay line combines a multi-tap delay circuit with the Gray code multiplexer. Specifically, the multi-tap delay circuit provides a plurality-of sequentially ordered delayed output signals on a plurality of sequentially ordered output terminals. The Gray code multiplexer has a plurality of input terminals coupled to the sequentially ordered delayed output terminals. The Gray code multiplexer is controlled by driving a Gray code value onto the control terminals of the Gray code multiplexer to select a specific delayed output terminal of the multi-tap delay circuit. The delay provided by the delay line is increased by incrementing the Gray code value on the control terminals of the Gray code multiplexer and decreased by decrementing the Gray code value on the control terminals. Race conditions on the control lines are eliminated when incrementing or decrementing the Gray code value by one.

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First Claim