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Abstract

A timing circuit to adjust a data strobe signal received from a synchronous memory includes a delay circuit to adjustably delay the data strobe signal and to generate a delayed data strobe signal, a clock capture register to sample the delayed data strobe signal and to generate a sampled clock signal, a data capture register to sample a read data signal from the synchronous memory and to generate a sampled data signal, and an analysis circuit to determine a timing relationship between the sampled clock signal and the sampled data signal and to adjust the delay circuit based on the determined timing relationship. By way of example, the determined timing relationship may be used to delay the read data strobe signal so that it transitions (e.g., from a low state to a high state) in the middle of the data signal's data eye.

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First Claim