Method and system for re-routing interconnects within an integrated circuit design having blockages and bays
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United States of America Patent
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Jun 4, 2002
Grant Date -
N/A
app pub date -
Dec 17, 1999
filing date -
Dec 17, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and system for re-routing interconnects within an integrated circuit design having blockages and bays is disclosed. A net within the integrated circuit design is initially decomposed into multiple two-paths. The net includes interconnects previously routed by utilizing a Steiner tree routing algorithm. Next, a cost associated with each of the two-paths is calculated. A two-path having a a high cost is subsequently selected and re-routed with a lower cost two-path.
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