Panel stacking of BGA devices to form three-dimensional modules
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United States of America Patent
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Jun 11, 2002
Grant Date -
N/A
app pub date -
Jun 21, 2000
filing date -
Jun 21, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers is electrically connected to the third conductive pattern of the transposer layer.
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