Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
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United States of America Patent
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Jun 11, 2002
Grant Date -
N/A
app pub date -
Jun 5, 1998
filing date -
Jun 5, 1998
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Abstract
A system and method for providing a burst sequence of data in a desired data ordering in response to a request packet. The burst sequence of data includes a plurality of data blocks and the request packet includes one or more data ordering bits which define a data ordering. The system includes one or more random access memory modules. Each random access memory module includes a memory array having a plurality of memory cells organized in an array of rows and columns, a row address decoder connected to the memory array for generating a row address which addresses one of the rows of the memory array, and a column address decoder connected to the memory array for generating a column address which addresses one of the columns of the memory array. The column address decoder includes data ordering control logic for placing data blocks retrieved from the memory array within the burst sequence as a function of the data ordering bits in the request packet such that consecutive burst sequences can be transferred in different data orderings.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT | 633 WEST FIFTH STREET 24TH FLOOR LOS ANGELES CA 90071 |
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Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Ryan, Kevin J | Eagle, ID | 106 | 3699 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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