US Patent No: 6,408,422

Number of patents in Portfolio can not be more than 2000

Method for remapping logic modules to resources of a programmable gate array

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Abstract

A method is provided for remapping logic modules to resources of a programmable gate array. Connections are specified between at least two logic modules, wherein each module has a respective floorplan that includes a set of circuit elements. A first set of resources of the programmable gate array is compared to a second set of resources, wherein the second set of resources are those resources required by the sets of circuit elements. If the first set of resources covers the second set of resources, the floorplans of the logic modules are combined into a single floorplan that maps to the first set of resources.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
XILINX, INC.SAN JOSE, CA3059

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hwang, L James Menlo Park, CA 33 501
Patterson, Cameron D Blacksburg, VA 16 306

Cited Art

Patent Info (Count) # Cites Year
 
XILINX, INC. (6)
5,499,192 Method for generating logic modules from a high level block diagram 108 1994
6,078,736 Method of designing FPGAs for dynamically reconfigurable computing 125 1997
5,995,744 Network configuration of programmable circuits 41 1998
6,216,258 FPGA modules parameterized by expressions 60 1998
6,237,129 Method for constraining circuit element positions in structured layouts 12 1998
6,243,851 Heterogeneous method for determining module placement in FPGAs 36 1998
 
LSI LOGIC CORPORATION (4)
4,918,614 Hierarchical floorplanner 180 1987
5,568,395 Modeling and estimating crosstalk noise and detecting false logic 78 1994
5,636,125 Computer implemented method for producing optimized cell placement for integrated circiut chip 141 1995
6,216,252 Method and system for creating, validating, and scaling structural description of electronic device 180 1996
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
4,554,625 Method for generating an optimized nested arrangement of constrained rectangles 69 1983
5,602,754 Parallel execution of a complex task partitioned into a plurality of entities 24 1995
5,946,486 Apparatus and method for tracing entries to or exits from a dynamic link library 52 1996
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (3)
5,519,630 LSI automated design system 39 1994
5,754,441 LSI Automated design system 30 1996
5,892,678 LSI design automation system 43 1997
 
NXP B.V. (3)
5,491,640 Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication 85 1994
5,519,627 Datapath synthesis method and apparatus utilizing a structured cell library 78 1994
6,170,080 Method and system for floorplanning a circuit design at a high level of abstraction 27 1997
 
VLSI TECHNOLOGY, INC. (3)
5,841,663 Apparatus and method for synthesizing integrated circuits using parameterized HDL modules 193 1995
5,774,370 Method of extracting implicit sequential behavior from hardware description languages 41 1995
5,612,893 Method and apparatus for compacting integrataed circuits with transistor sizing 34 1996
 
CADENCE DESIGN SYSTEMS, INC. (2)
5,604,680 Virtual interface representation of hierarchical symbolic layouts 59 1994
5,838,583 Optimized placement and routing of datapaths 195 1996
 
LATTICE SEMICONDUCTOR CORPORATION (2)
5,818,254 Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices 64 1995
5,594,657 System for synthesizing field programmable gate array implementations from high level circuit descriptions 76 1995
 
UNIVERSITY OF WASHINGTON (2)
5,208,491 Field programmable gate array 344 1992
6,023,742 Reconfigurable computing architecture for providing pipelined data paths 192 1997
 
ACTEL CORPORATION (1)
5,640,327 Apparatus and method for partitioning resources for interconnections 107 1996
 
ADVANCED MICRO DEVICES, INC. (1)
6,167,363 Design for a simulation module using an object-oriented programming language 25 1998
 
ADVANCED TELECOMMUNICATIONS RESEARCH INSTITUTE INTERNATIONAL (1)
5,615,124 Autonomous evolution type hardware design system 12 1994
 
ALTERA CORPORATION (1)
6,080,204 Method and apparatus for contemporaneously compiling an electronic circuit design by contemporaneously bipartitioning the electronic circuit design using parallel processing 68 1997
 
ATMEL CORPORATION (1)
5,946,219 Method and system for configuring an array of logic devices 56 1996
 
CALLAHAN CELLULAR L.L.C. (1)
5,828,588 Parametrizable control module comprising first and second loadable counter, an electronic circuit comprising a plurality of such parametrized control modules, and a method for synthesizing such circuit 9 1996
 
CASCADE DESIGN AUTOMATION CORPORATION (1)
5,351,197 Method and apparatus for designing the layout of a subcircuit in an integrated circuit 35 1992
 
CHIP EXPRESS (ISRAEL) LTD. (1)
5,818,728 Mapping of gate arrays 38 1996
 
CODEGEAR LLC (1)
5,408,665 System and methods for linking compiled code with extended dictionary support 134 1993
 
FREESCALE SEMICONDUCTOR, INC. (1)
5,311,443 Rule based floorplanner 53 1992
 
FUJITSU VLSI LIMITED (1)
5,446,675 Developing method and apparatus of hierarchical graphic data for use in a semiconductor integrated circuit 15 1994
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
5,649,100 Network backplane interface having a network management section for managing and configuring networks on the backplane based upon attributes established in a parameter table 37 1994
 
MATRA HACHETTE SA (1)
5,717,928 System and a method for obtaining a mask programmable device using a logic description and a field programmable device implementing the logic description 34 1990
 
MICROSOFT CORPORATION (1)
6,059,838 Method and system for licensed design and use of software objects 47 1999
 
RENESAS ELECTRONICS CORPORATION (1)
5,394,338 Module cell generating device for a semiconductor integrated circuit 11 1991
 
SAMSUNG ELECTRONICS CO., LTD. (1)
5,519,629 Tileable gate array cell for programmable logic devices and gate array having tiled gate array cells 79 1995
 
SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER (1)
6,026,228 Integrated circuit design method, database apparatus for designing integrated circuit and integrated circuit design support apparatus 34 1997
 
SILICON GRAPHICS INTERNATIONAL, CORP. (1)
5,757,658 Procedure and system for placement optimization of cells within circuit blocks by optimizing placement of input/output ports within an integrated circuit design 36 1996
 
SYNOPSYS, INC. (1)
5,937,190 Architecture and methods for a hardware description language source level analysis and debugging system 78 1995
 
UNISYS CORPORATION (1)
5,696,693 Method for placing logic functions and cells in a logic design using floor planning by analogy 51 1995
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
5,838,165 High performance self modifying on-the-fly alterable logic FPGA, architecture and method 225 1996

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
XILINX, INC. (19)
6,530,070 Method of constraining non-uniform layouts using a uniform coordinate system 9 2001
6,487,708 Hierarchical location constraints for programmable layouts 12 2001
7,058,921 Method and system for resource allocation in FPGA-based system-on-chip (SoC) 40 2002
7,073,149 System for representing the logical and physical information of an integrated circuit 7 2004
7,146,595 Data structures for representing the logical and physical information of an integrated circuit 4 2004
7,120,892 Process for adjusting data structures of a floorplan upon changes occurring 4 2004
7,117,473 System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks 3 2004
7,437,695 Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices 4 2005
7,370,302 Partitioning a large design across multiple devices 2 2005
7,418,686 System for representing the logical and physical information of an integrated circuit 4 2005
7,584,448 Constructing a model of a programmable logic device 2 2006
7,536,668 Determining networks of a tile module of a programmable logic device 3 2006
7,472,370 Comparing graphical and netlist connections of a programmable logic device 1 2006
7,451,420 Determining reachable pins of a network of a programmable logic device 0 2006
7,451,423 Determining indices of configuration memory cell modules of a programmable logic device 1 2006
7,451,424 Determining programmable connections through a switchbox of a programmable logic device 1 2006
7,451,425 Determining controlling pins for a tile module of a programmable logic device 2 2006
7,673,271 Enhancing relocatability of partial configuration bitstreams 4 2006
7,873,927 Partitioning a large design across multiple devices 0 2008
 
ALTERA CORPORATION (4)
7,082,592 Method for programming programmable logic device having specialized functional blocks 7 2003
7,441,223 Method and apparatus for performing synthesis to improve density on field programmable gate arrays 0 2005
7,669,157 Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches 1 2006
8,250,505 Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches 0 2009
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
6,996,795 Data processing in digital systems 1 2003
7,353,486 Data processing in digital systems 0 2005
 
SUN MICROSYSTEMS, INC. (2)
6,516,449 Methodology to create integrated circuit designs by replication maintaining isomorphic input output and fault behavior 13 2001
6,735,754 Method and apparatus to facilitate global routing for an integrated circuit layout 10 2002
 
NANGATE A/S (1)
8,271,930 Optimizing a circuit design library 2011
 
SYNOPSYS, INC. (1)
6,738,953 System and method for memory characterization 12 2002

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