Multilayered wiring board, a production process for, and semiconductor device using, the same
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United States of America Patent
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Jun 25, 2002
Grant Date -
Apr 18, 2002
app pub date -
Dec 14, 2000
filing date -
Dec 17, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A multilayered wiring board comprising, at least, two wiring layers and an interlaminar insulating layer, in which said wiring board further has, incorporated therein, at least one capacitor element which comprises a sandwiched structure of a lower electrode-forming metallic layer having formed thereon at least one recess portion, a dielectric layer formed over the lower electrode-forming metallic layer, and an upper electrode-forming metallic layer formed over the dielectric layer, and its production process. The semiconductor device comprising the multilayered wiring board having mounted thereon a semiconductor element is also disclosed.
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