Multi-state nonvolatile semiconductor memory device which is capable of regularly maintaining a margin between threshold voltage distributions
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United States of America Patent
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Jun 25, 2002
Grant Date -
N/A
app pub date -
Oct 31, 2000
filing date -
Nov 1, 1999
priority date (Note) -
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Abstract
A nonvolatile semiconductor memory device of the present invention has an array that includes a bit line, a plurality of word lines arranged perpendicularly to the bit line and a plurality of memory cells each arranged at intersections of the bit line and the word lines. In the nonvolatile semiconductor memory device is further provided a storage circuit and a program data judging circuit. The storage circuit has at least two latches each of which is connected to a corresponding input/output line and latches data. The program data judging circuit judges whether logic states of data latched in the latches indicate a programming or a program-inhibition of a selected memory cell, and sets the bit line to a program voltage or a program inhibition voltage according to a judgment result.
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