COMPACTING METHOD OF CIRCUIT LAYOUT BY MOVING COMPONENTS USING MARGINS AND BUNDLE WIDTHS IN COMPLIANCE WITH THE DESIGN RULE, A DEVICE USING THE METHOD AND A COMPUTER PRODUCT ENABLING PROCESSOR TO PERFORM THE METHOD
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United States of America Patent
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Jun 25, 2002
Grant Date -
N/A
app pub date -
Feb 1, 2000
filing date -
Feb 2, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A layout compaction method adapted to be embodied in computer program product and adapted for compacting a circuit layout having a plurality of layers on which moving objects form layer patterns, wherein the moving objects comprising components and wires. The method assumes a graph problem under condition which prevent the compacted result from violation of the design rule, and then, solves the graph problem to determine a moving order, a moving direction, and a moving distance of each component for moving the components to thereby perform the compacting the circuit layout. After that, the method moves each component according to the moving order, the moving direction and the moving distance to obtain a compacted circuit layout.
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