Importance

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Abstract

A memory expansion module including multiple memory banks and a bank control circuit is disclosed. In one embodiment, a memory module includes a printed circuit board with a connector edge adapted for insertion in an expansion socket of a computer system. Mounted upon the circuit board is a plurality of memory chips, typically Dynamic Random Access Memory (DRAM) chips, which make up an upper bank and a lower bank of memory. A buffer circuit is mounted upon the printed circuit board, for the purpose of driving address signals, Column Address Strobe (CAS) signals, and write enable signals to each of the memory chips. Also mounted upon the printed circuit board is a bank control circuit, which is coupled to the memory chips. An address signal is used as a bank selection input to the bank control circuit, which will drive Row Address Strobe (RAS) signals to the memory chips of the selected memory bank. The bank control circuit is further configured to drive RAS signals to both banks simultaneously during CBR (CAS before RAS) refresh operations, which occur when a CAS signal is asserted before a RAS signal.

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First Claim