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Abstract

A memory system, which can improve the operation speed of a data bus and is suitable for widening bandwidth by extending the width of the data bus, and memory modules used for the memory system are provided. In the memory system, data buses of a first channel and data buses of a second channel are extended from a memory controller and are arranged on the left and right of a common control and address bus, respectively. Memory modules of a first group are loaded in the data buses of the first channel and memory modules of a second group are loaded in the data buses of the second channel. Also, in the memory system, the memory modules share the common control and address bus positioned in the center. Also, the memory modules are arranged so that some parts of the memory modules overlap each other and that the memory modules of the first group and the memory modules of the second group cross each other. Each of the memory modules includes a plurality of memory devices mounted on the memory module, a signal input and output portion positioned on a side of the memory module, the signal input and output portion for connecting the memory module to a connector on a system board, a buffer mounted on the memory module, and a control and address bus connected between the signal input and output portion and the buffer. The memory devices are sequentially connected to the output line of the buffer so that a signal that passed through the control and address bus is input to the respective memory devices at time intervals through the buffer.

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