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Abstract

Improved operating system architecture for an implantable medical device incorporating adiabatic clock-powered logic alone or in conjunction with conventional clocked logic or self-timed logic for reducing power consumption and increasing and improving processing capabilities is disclosed. The adiabatic clock-powered logic is employed to implement digital signal processors (DSPs) including analog to digital (ADC) signal converters, a state machine or the components of microprocessor cores, e.g., the CPU, arithmetic logic units (ALU), on-chip RAM and ROM and data and control buses, and other logic units, e.g., additional RAM and ROM, a direct memory address (DMA) controller, a block mover/reader, a cyclic redundancy code (CRC) calculator, and certain uplink and downlink telemetry signal processing stages. The adiabatic clocked CMOS logic is incorporated into the same IC or ICs with clocked CMOS logic and provides manufacturing economies.

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First Claim