Method and device for executing by a single processor several functions of different criticality levels, operating with high security
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United States of America Patent
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Jul 2, 2002
Grant Date -
N/A
app pub date -
Aug 25, 1999
filing date -
Feb 25, 1997
priority date (Note) -
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Abstract
A processor for executing several functions. The processor has access to an addressable space including memories for program and for data and input/output registers. The method of operation includes the allocation of a right of access to each function, the dividing of the addressable space and of partitions, each associated with the access right of a function, and the dividing of the time of use of the processor into cyclic time slices associated with the access right of a function. At the start of each new time slice, it is confirmed that the processor has terminated the execution of the previous function. The method further includes the activation of the tasks of the corresponding function. During each access by a processor to an addressable area, the access right of the current time slice is compared with that associated with the accessed are, with an error signal being transmitted in case of an inconsistency.
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