Method and system for performing capacitance estimations on an integrated circuit design routed by a global routing tool
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 2, 2002
Grant Date -
N/A
app pub date -
Sep 17, 1999
filing date -
Sep 17, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for performing capacitance estimations on an integrated circuit design routed by a global routing tool is disclosed. Routing areas and pin locations of a net within an integrated circuit design are initially obtained from a global routing tool. Common boundaries among the routing areas are then defined. Before the performance of a detailed routing step, congestion information furnished by the global routing tool is utilized to perform probabilistic capacitance calculations for an interconnect that can be routed within the routing areas via the defined common boundaries to connect the pin locations.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully