Method and apparatus for forming an integrated circuit electrode having a reduced contact area
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United States of America Patent
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Jul 16, 2002
Grant Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Jun 7, 1995
priority date (Note) -
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Abstract
A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.
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