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Abstract

A video processor has motion estimation, pixel processing, and general processing modes. In the processor, an internal memory acts as a buffer containing a search window in motion estimation mode and as a scratch pad in pixel and general processing modes. Another internal memory acts as a buffer for a reference block in search mode and as a register file in pixel and general processing modes. Both internal memories provide parallel pixel-size data elements in pixel processing mode and larger data elements in general processing mode. An ALU in the processor has multiple slices that operate independently for parallel processing in motion estimation and pixel processing modes and cooperatively to provide a larger data width for general purpose processing mode. The ALU includes a line buffer, and each ALU slice includes two adders with operand selection circuitry that enables on-the-fly compression and half-pixel interpolation processes, single cycle determination of absolute differences, and arithmetic operations.

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First Claim