Method and apparatus for diagnosing memory using self-testing circuits
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United States of America Patent
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Jul 16, 2002
Grant Date -
N/A
app pub date -
Mar 9, 2000
filing date -
Mar 9, 2000
priority date (Note) -
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Abstract
A method and apparatus for diagnosing memory using self--testing circuits. A comparator compares actual data output from a RAM with expected output generated by built--in self--testing (BIST) circuitry. The comparator outputs a resulting initial fail vector which is subsequently input into a compressor. The compressor performs multiple logical operations on the initial fail vector to compress or reduce the bit--width of the initial fail vector, resulting in a compressed fail vector. Once generated, the compressed fail vector is fed to I/O terminals of the integrated circuit (IC) forming a stream of bits to be recorded by test equipment external to the IC. The recorded compressed fail vector is then utilized to reconstruct the initial fail vector that was generated by the bit comparator.
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