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Abstract

A method for shallow trench isolation formation having a thick un-biased HDP USG liner layer to reduce HDP-CVD induced defects is described. Trenches are etched through an etch stop layer into a semiconductor substrate. The semiconductor substrate is thermally oxidized to form a thermal liner layer within the isolation trenches. The isolation trenches are filled using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein the HDP-CVD process comprises: first depositing a first liner layer overlying the thermal liner layer wherein no bias power is supplied during the first depositing step and wherein the first liner layer has a thickness of between 200 and 400 Angstroms, second depositing a second liner layer using low bias power, and third depositing a gap filling layer overlying the second liner layer to fill the isolation trenches. The gap filling layer is polished back overlying the etch stop layer. The etch stop layer is removed to complete planarized shallow trench isolation regions in the manufacture of an integrated circuit device.

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First Claim