Memory device having a variable data output length and a programmable register
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United States of America Patent
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Jul 30, 2002
Issued Date -
N/A
app pub date -
Feb 27, 2001
filing date -
Apr 18, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing a value which is representative of a number of cycles of an external clock signal to transpire after which the memory device responds to a read request. The method further includes providing block size information to the memory device, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes receiving the amount of data, after the number of clock cycles of the external clock signal transpire.
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