SRAM controller for parallel processor architecture including address and command queue and arbiter
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United States of America Patent
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Jul 30, 2002
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N/A
app pub date -
Aug 31, 1999
filing date -
Aug 31, 1999
priority date (Note) -
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Abstract
A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.
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