US Patent No: 6,427,222
Number of patents in Portfolio can not be more than 2000
Inter-dice wafer level signal transfer methods for integrated circuits
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Jul 30, 2002
Issued date -
Sep 30, 1997
filing date -
08/941,786
serial no -
In Force
status
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Abstract
The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a series of inter-dice data transfers. It is therefore possible to use a small number of small area metal lines to support wafer level parallel processing activities. External connections are provided by a small number of bonding pads on each wafer. The load on each external bounding pad is by far lower than that of prior art wafer level connections. These inter-dice data transfer mechanism also can be programmed to avoid defective circuitry. This invention has been used to support wafer level functional tests and wafer level burn-in tests. A Testing system of the present invention can test thousands of dice in parallel using simple testing equipment. Testing costs for integrated circuits are therefore reduced dramatically. The present application also make it possible to build large area IC containing multiple dice. Extremely powerful products are realized using parallel processing capability of such multiple die integrated circuits.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,399,505 Method and apparatus for performing wafer level testing of integrated circuit dice | 102 | 1993 | |
| 5,504,369 Apparatus for performing wafer level testing of integrated circuit dice | 82 | 1994 | |
| 5,617,531 Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor | 132 | 1995 | |
| 5,593,903 Method of forming contact pads for wafer level testing and burn-in of semiconductor dice | 70 | 1996 | |
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| 5,442,282 Testing and exercising individual, unsingulated dies on a wafer | 102 | 1992 | |
| 5,532,174 Wafer level integrated circuit testing with a sacrificial metal layer | 48 | 1994 | |
| 5,489,538 Method of die burn-in | 80 | 1995 | |
| 5,838,163 Testing and exercising individual, unsingulated dies on a wafer | 75 | 1995 | |
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| 5,949,242 Method and apparatus for testing unpackaged semiconductor dice | 41 | 1996 | |
| 6,049,977 Method of forming electrically conductive pillars | 15 | 1997 | |
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| 5,512,710 Multilayer package with second layer via test connections | 10 | 1992 | |
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| 5,701,666 Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located on a product wafer | 158 | 1997 | |
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| 5,732,209 Self-testing multi-processor die with internal compare points | 116 | 1996 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jan 30, 2014 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |