Method and apparatus for reducing direct memory access transfers using smart coalescing

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United States of America Patent

PATENT NO 6430628
SERIAL NO

09207461

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Abstract

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One embodiment of the invention comprises a method and apparatus for managing data transfers from memory to an input/output device where the data is stored in memory as data fragments. A first list of memory locations for the fragments is received. A sub-set of fragments for copying to at least one of a first and second buffer is selected based on fragment size. A request to copy the selected sub-set of fragments to the at least one first and second buffer is sent. A request to lock down any unselected fragments is sent. A second list of memory locations for the fragments is created. The second list comprises memory locations for the at least one first and second buffer and locked down fragments.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Connor, Patrick Portland, OR 97 1660

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