Importance

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Abstract

An embodiment of a memory controller that improves processor to graphics device throughput by reducing the frequency of retries of postable write transaction requests is disclosed. The memory controller includes a posted write buffer and a timeout counter. The memory controller is coupled to a processor via a host bus and is also coupled to a graphics device via a graphics bus. If the posted write buffer is unavailable when a first postable write transaction request is received by the memory controller, the memory controller stalls the host bus and waits for the posted write buffer to become available. If a second transaction request is received while the posted write buffers are unavailable, the timeout counter is initiated. If the posted write buffer becomes available before the timeout counter expires, the first postable write transaction request is completed. If, however, the timeout counter expires before the posted write buffer becomes available, the memory controller issues a retry response to the processor, indicating to the processor that the first postable write transaction request must be reissued at a later time.

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First Claim