METHOD AND SYSTEM FOR GENERATION AND DISTRIBUTION OF SUPPLY VOLTAGES IN MEMORY SYSTEMS
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United States of America Patent
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Aug 13, 2002
Grant Date -
Aug 22, 2002
app pub date -
Feb 16, 2001
filing date -
Feb 16, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are described. The various voltage levels can be produced by voltage generation circuitry (e.g., charge pump and/or regulator circuitry) within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect, charge pump and/or regulator circuits are provided within at most one of the memory blocks of a memory system (unless back-ups are provided for fault tolerance), and a power bus is used to distribute the generated voltage levels to other of the memory blocks. According to another aspect, a memory controller generates multiple supply voltage levels that are distributed (e.g., via a power bus) to each of the memory blocks.
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