Hardware or software architecture implementing self-biased conditioning

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United States of America Patent

PATENT NO 6434540
SERIAL NO

09234178

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An architecture, which may be embodied in hardware, software or a combination of the two, implementing self-biased conditioning and having at least one primary response network (1) comprising: a single activation node (X) responding to a first value of an input signal received from at least one sensor (S.sub.A) by outputting a trigger signal (O.sub.1), one or more motor centers (M) receiving the trigger signal (O.sub.1) and having an innate response to generate an output signal (O.sub.3) for activating an actuator (C.sub.1), means (y.sup.+, y.sup.-) for applying positive and negative reinforcement signals to the motor center (M) to promote or inhibit the response of the motor center (M) to the trigger signal (O.sub.1), one or more expectation nodes (Y) receiving an input signal from at least one second sensor (S.sub.B), and generating an output signal (O.sub.2) indicating when the generation of said output signal (O.sub.3) for activating the actuator is not appropriate; and an associative memory (2) generating said positive and negative reinforcement signals in response to a determination that the response of the motor center requires promotion or inhibition.

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Patent Owner(s)

Patent OwnerAddress
SONY FRANCE S A20-26 RUE MOREL 92110 CLICHY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Numaoka, Chisato Kanagawa, JP 25 745

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