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Abstract

A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated write address with a currently-generated read address and a next-to-be-used read address. The current write address and current read address are transmitted from a write address counter and a read address counter, respectively, to a flag control circuit. The flag control circuit includes registers for storing Gray-code versions of the current write address, the current read address, and the next-to-be-used read address, which is determined from the current read address. The flag control circuit generates intermediate ALMOST_EMPTY and ALMOST_FULL signals when the FIFO memory is one data value from being 'empty' and 'full', respectively. These intermediate signals are used to generate FULL and EMPTY control signals immediately after the FIFO memory enters a 'full' or 'empty' condition. A status circuit re-synchronizes a binary read address to the write clock signal, then subtracts the write-synchronized read address from the binary write address to accurately determine the amount of data in the FIFO memory.

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First Claim