Methods and apparatus for improving system performance with a shared cache memory

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United States of America Patent

PATENT NO 6434672
SERIAL NO

09515727

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Abstract

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A computer system comprising a plurality of processors each having dedicated cache memories, another level of cache shared by the plurality of caches, and a main memory. The processors and the shared cache act as peers on a bus located between the processors and main memory. All data placed upon the bus by the main memory as a result of a read transaction are written into the shared cache. The shared cache does not initiate any transactions.

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Patent Owner(s)

Patent OwnerAddress
HEWLETT-PACKARD DEVELOPMENT COMPANY L P10300 ENERGY DRIVE SPRING TX 77389

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gaither, Blaine D Ft. Collins, CO 60 1392

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