Encryption processor with shared memory interconnect
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United States of America Patent
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Aug 13, 2002
Issued Date -
N/A
app pub date -
Jun 1, 2000
filing date -
Feb 27, 1998
priority date (Note) -
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Abstract
An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.
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