Importance

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Abstract

After a layout for a semiconductor device including power and ground lines has been defined, patterns for bypass capacitors, which will be located under the power lines, are created. In this case, a pattern for a semiconductor device, where a bypass capacitor array is inlaid and substrate contacts are located under ground lines, is defined based on design rules input. Next, power lines are extracted and resized. Thereafter, logical operations are performed to place the bypass capacitors and the bypass capacitors are resized. Subsequently, logical operations are performed to define interconnecting diffused layers and the diffused layers are resized. Since the patterns for the power lines have already been defined before the patterns for the bypass capacitors are created, the patterns for the bypass capacitors to be placed under the power lines can be defined automatically. Thus, a pattern for a miniaturized semiconductor device with reduced power supply noise can be created automatically.

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First Claim