Location based timing scheme in memory design

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United States of America Patent

PATENT NO 6434736
SERIAL NO

09351100

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Abstract

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A method and apparatus for improving the access time of a memory device is described. The location based timing scheme utilizes a subset of the address bits to adjust the timing of the sense amplifier enable in order to achieve a faster read of the information stored in the memory cell.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Burgess, Jr Richard J Phoenix, AZ 4 182
Miller, Jay B Chandler, AZ 8 206
Schaecher, Mark A Phoenix, AZ 5 192

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