Method for achieving copper fill of high aspect ratio interconnect features

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United States of America Patent

PATENT NO 6436267
SERIAL NO

09650108

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.

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Patent Owner(s)

  • APPLIED MATERIALS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Carl, Daniel A Pleasanton, CA 29 903
Chen, Liang San Jose, CA 851 7999
Cheung, Robin Cupertino, CA 71 3113
Chin, Barry Saratoga, CA 33 1297
Ding, Peijun San Jose, CA 132 3330
Dordi, Yezdi Palo Alto, CA 117 2660
Hashim, Imran San Jose, CA 125 2654
Hey, Peter Sunnyvale, CA 12 830
Sinha, Ashok K Palo Alto, CA 56 4503

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