Method for mounting an integrated circuit having reduced thermal stresses between a bond pad and a metallic contact

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United States of America Patent

PATENT NO 6436735
SERIAL NO

09630247

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Abstract

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A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system while reducing contact degradation due to stress that results from differences in the coefficients of thermal expansion of the various components during thermal cycling

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Patent Owner(s)

Patent OwnerAddress
TECHNOLOGY IP HOLDINGS3259 KIFER ROAD SANTA CLARA CA 95051

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Avery, George E Saratoga, CA 6 131
Beal, Sam Mountain View, CA 4 107
Brown, Sammy K Los Gatos, CA 16 266
Goetz, Martin P Discovery Bay, CA 17 217
Todd, Tom L San Jose, CA 4 107
Wiggin, Andrew K San Carlos, CA 6 131

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