Method for making an interconnect layer and a semiconductor device including the same
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United States of America Patent
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Aug 20, 2002
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N/A
app pub date -
Jan 18, 2000
filing date -
Jan 18, 2000
priority date (Note) -
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Abstract
A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout. The method further includes adding dummy fill features to each layout region to obtain a desire density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added, and each layout region has a uniform density.
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