Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
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United States of America Patent
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Aug 20, 2002
Grant Date -
N/A
app pub date -
Jul 10, 1998
filing date -
Jul 10, 1997
priority date (Note) -
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Abstract
A wiring structure for effectively reducing wiring capacitance, and a method of forming the wiring structure is disclosed. An underlying film having a dielectric constant lower than that of silicon oxide is formed on at least side surfaces of the wires of a wiring layer and a low dielectric constant film having an even lower dielectric constant is formed between the wires. Further, the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.
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