Bumpless flip chip assembly with strips-in-via and plating
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United States of America Patent
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Aug 20, 2002
Grant Date -
Jan 17, 2002
app pub date -
Dec 16, 1999
filing date -
Dec 17, 1998
priority date (Note) -
Expired
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Abstract
A flip chip assembly, and methods of forming the same, including a single or multi-layer substrate having a plurality of via holes in which pre-formed strips or leads inside the via holes serve as the connections between the semiconductor device and substrate circuitry. The assembling steps include attaching an integrated circuit (IC) chip having a plurality of input/output terminal pads to a rigid or flexible substrate having a plurality of leads extending from the patterned circuitry traces and hanging inside a plurality of through via holes. The via holes are aligned with and expose the terminal pads After attachment, an electrically conductive material connects the leads to the IC terminal pads through electrolytic plating, electroless (chemical) plating or solder re-flow processes. The conductive material provides mechanical support as well as electrical continuity between the IC chip and the circuitry of the substrate.
First Claim
Family
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- LIN, CHARLES W.C.
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Lin, Charles Wen Chyang | 55 Cairnhill Road #21-04 Cairnhill Plaza, Singapore, SG | 6 | 107 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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