Storage device buffer access control in accordance with a monitored latency parameter

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United States of America Patent

PATENT NO 6438629
SERIAL NO

09243190

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Abstract

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A memory subsystem includes a buffer, a storage device, a buffer access determining mechanism, a request communicator, and a disk input/output subsystem. The buffer comprises a buffer channel having a limited data transfer rate. The storage device comprises a read/write mechanism and non-volatile storage media. The determining mechanism determines when a given client is to be given access to the buffer channel. It comprises a latency monitor for monitoring a latency parameter indicative of the buffer channel access latency for the given client and a buffer access controller for controlling when the given client is given access to the buffer channel in accordance with the monitored latency parameter. The request communicator couples requestors to the buffer access determining mechanism. The requesters request the buffer access determining mechanism to give clients access to the buffer channel. When clients are given access to the buffer channel, they write data to or read data from the buffer via the buffer channel. The disk input/output subsystem exchanges data between the buffer and the storage media.

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Patent Owner(s)

Patent OwnerAddress
MAXTOR CORPORATION211 RIVER OAKS PARKWAY SAN JOSE CA 95134 UNITED STATES OF AMERICA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Buch, Bruce D Westboro, MA 27 694
Huebner, Geoffrey L Hopkinton, MA 1 11

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