Programmatic iteration scheduling for parallel processors

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United States of America Patent

PATENT NO 6438747
SERIAL NO

09378393

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Abstract

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A parallel compiler maps iterations of a nested loop to processor elements in a parallel array and schedules a start time for each iteration such that the processor elements are fully utilized without being overloaded. The compiler employs an efficient and direct method for generating a set of iteration schedules that satisfy the following constraints: no more than one iteration is in initiated per processor element in a specified initiation interval, and a new iteration begins on each processor element nearly every initiation interval. Since the iteration scheduling method efficiently generates a set of schedules, the compiler can select an iteration schedule that is optimized based on other criteria, such as memory bandwidth, local memory size of each processor element, estimated hardware cost of each processor element, etc. The iteration scheduling method is useful for compilers where the underlying architecture is fixed, as well as for an automated processor array synthesis system where the nested loop is converted into a set of parallel processes for synthesis into a parallel processor array.

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Patent Owner(s)

  • SAMSUNG ELECTRONICS CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Darte, Alain Lyons, FR 5 207
Rau, Bantwal Ramakrishna Los Altos, CA 4 171
Schreiber, Robert S Palo Alto, CA 19 795

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