Frequency-doubling delay locked loop
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United States of America Patent
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Aug 27, 2002
Grant Date -
N/A
app pub date -
May 1, 2000
filing date -
Apr 30, 1999
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.
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